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AltiVec Instruction Cross-Reference

This table provides a convenient cross-reference of C language intrinsics, processor instruction names and descriptive names for each instruction in the AltiVec instruction set, as well as the number of arguments and the hardware unit used.

The Instruction Cross-Reference table can be downloaded in the MS-Excel 98 format.

Instruction timings can be determined from the hardware unit according to the following table:

Hardware Unit Pipeline Depths
7400/7410
7450/7455
970 (G5)

Load/store unit (LSU)

3
3
4**

Vector Simple Integer Unit (VSIU)

1
1
2***

Vector Complex Integer Unit (VCIU)

3
4
5***

Vector Floating Point Unit (VFPU)

4 (5)*
4 (5)[2]*
8***

Vector Permute Unit (VPERM)

1
2
2**

*The VFPU takes an extra cycle if Java mode is turned on.
(It is off by default on MacOS X, but on by default on MacOS 9.)
**An extra cycle latency is required if the the data is next used in VCIU/VSIU/VFPU.
***An extra cycle latency is required if the data is next used in VPERM
[2]: Some FP-related VSIU instructions were moved to the VFPU for later G4.
These only take two cycles instead of the usual 4 (5).

In the table below, many of the C language instructions have several corresponding assembly language instructions.The C compiler determines the proper assembly instruction by the type of the argument(s).

Processor instruction suffixes follow this convention:

ub

unsigned byte

uh

unsigned halfword

uw

unsigned word

sb

signed byte

sh

signed halfword

sw

signed word

fp

floating point

m

modulo

s

saturate

Load and Store Instructions
Software Directed Prefetch Instructions
Data Manipulation Instructions
Arithmetic Instructions
Logical Instructions
Compare Instructions

C Intrinsic
Processor Instruction
Instruction Name

Arguments

Unit

Load and Store Instructions

vec_ld

lvx

load vector indexed

2

LSU

vec_ldl

lvxl

load vector indexed LRU

2

LSU

vec_lde

lvebx

load vector element indexed

2

LSU

lvehx

lvewx

vec_lvsl

lvsl

load vector for shift left

2

LSU

vec_lvsr

lvsr

load vector for shift right

2

LSU

vec_st

stvx

store vector indexed

3

LSU

vec_stl

stvxl

store vector indexed LRU

3

LSU

vec_ste

stvebx

store vector element indexed

3

LSU

stvehx

stvewx

Software Directed Prefetch Instructions

vec_dst

dst

data stream touch

3

LSU

vec_dstt

dstt

data stream touch transient

3

LSU

vec_dstst

dstst

data stream touch for store

3

LSU

vec_dststt

dststt

data stream touch for store transient

3

LSU

vec_dss

dss

data stream stop

1

LSU

vec_dssall

dssall

data stream stop all

0

LSU

Data Manipulation Instructions

vec_perm

vperm

vector permute

3

VPERM

vec_sel

vsel

vector conditional select

3

VSIU

vec_sr

vsrb

vector shift right

2

VSIU

vsrh

vsrw

vec_sra

vsrab

vector shift right algebraic

2

VSIU

vsrah

vsraw

vec_srl

vsr

vector shift right logical

2

VSIU VPERM

vec_sro

vsro

vector shift right by octet

2

VSIU VPERM

vec_sl

vslb

vector shift left

2

VSIU

vslh

vslw

vec_sll

vsl

vector shift left logical

2

VSIU VPERM

vec_slo

vslo

vector shift left by octet

2

VSIU VPERM

vec_sld

vsldoi

vector shift left double by octet immediate

3

VPERM

vec_rl

vrlb

vector rotate left integer

2

VSIU

vrlh

vrlw

vec_mergeh

vmrghb

vector merge high

2

VPERM

vmrghh

vmrghw

vec_mergel

vmrglb

vector merge low

2

VPERM

vmrglh

vmrglw

vec_splat

vspltb

vector splat

2

VPERM

vsplth

vspltw

vec_splat_s8

vspltisb

vector splat signed byte

1

VPERM

vec_splat_s16

vspltish

vector splat signed halfword

1

VPERM

vec_splat_s32

vspltisw

vector splat signed word

1

VPERM

vec_splat_u8

vspltisb

vector splat unsigned byte

1

VPERM

vec_splat_u16

vspltish

vector splat unsigned halfword

1

VPERM

vec_splat_u32

vspltisw

vector splat unsigned word

1

VPERM

vec_mfvscr

mfvscr

move from vector status and control register

0

VSIU

vec_mtvscr

mtvscr

move to vector status and control register

1

VSIU

vec_pack

vpkuhum

vector pack modulo

2

VPERM

vpkuwum

vec_packpx

vpkpx

vector pack pixel

2

VPERM

vec_packs

vpkuhus

vector pack signed saturate

2

VPERM

vpkshss

vpkuwus

vpkswss

vec_packsu

vpkuhus

vector pack unsigned saturate

2

VPERM

vpkshus

vpkuwus

vpkswus

vec_unpackh

vupkhsb

vector unpack high

1

VPERM

vupkhpx

vupkhsx

vec_unpackl

vupklsb

vector unpack low

1

VPERM

vupklpx

vupklsh

Arithmetic Instructions

vec_abs

vspltisb
vsububm
vmaxsb

vector absolute value

1

 

vspltisb
vsubuhm
vmaxsh

vspltisb
vsubuwm
vmaxsw

vspltisw
vslw
vandc

vec_abss

vspltisb
vsubsbs
vmaxsb

vector absolute value saturated

1

 

vspltisb
vsubshs
vmaxsh

vspltisb
vsubsws
vmaxsw

vec_add

vaddubm

vector add modulo

2

VSIU

vadduhm

vadduwm

vaddfp

VFPU

vec_addc

vaddcuw

vector add & write carry-out

2

VSIU

vec_adds

vaddubs

vector add saturated

2

VSIU

vaddsbs

vadduhs

vaddshs

vadduws

vaddsws

vec_sub

vsububm

vector subtract modulo

2

VSIU

vsubuhm

vsubuwm

vsubfp

VFPU

vec_subc

vsubcuw

vector subtract and write carry-out

2

VSIU

vec_subs

vsububs

vector subtract saturated

2

VSIU

vsubsbs

vsubuhs

vsubshs

vsubuws

vsubsws

vec_mule

vmuleub

vector multiply even integer

2

VCIU

vmulesb

vmuleuh

vmulesh

vec_mulo

vmuloub

vector multiply odd integer

2

VCIU

vmulosb

vmulouh

vmulosh

vec_madd

vmaddfp

vector multiply-add float

3

VFPU

vec_madds

vmhaddshs

vector multiply-high and add saturate

3

VCIU

vec_mladd

vmladduhm

vector multiply-low and add modulo

3

VCIU

vec_mradds

vmhraddshs

vector multiply-high round and add saturate

3

VCIU

vec_msum

vmsumubm

vector multiply-sum modulo

3

VCIU

vmsumuhm

vmsummbm

vmsumshm

vec_msums

vmsumuhs

vector multiply-sum saturate

3

VCIU

vmsumshs

vec_sum4s

vsum4ubs

vector sum across 1/4 integer

2

VCIU

vsum4sbs

vsum4shs

vec_sum2s

vsum2sws

vector sum across 1/2 signed integer

2

VCIU

vec_sums

vsumsws

vector sum across signed integer

2

VCIU

vec_nmsub

vnmsubfp

vector negative multiply-subtract

3

VFPU

vec_avg

vavgub

vector average integer

2

VSIU

vavgsb

vavguh

vavgsh

vavguw

vavgsw

vec_max

vmaxub

vector maximum

2

VSIU

vmaxsb

vmaxuh

vmaxsh

vmaxuw

vmaxsw

vmaxfp

VSIU VFPU

vec_min

vminub

vector minimum

2

VSIU

vminsb

vminuh

vminsh

vminuw

vminsw

vminfp

VSIU VFPU

vec_round

vrfin

vector round to nearest

1

VFPU

vec_ceil

vrfip

vector round to ceiling

1

VFPU

vec_floor

vrfim

vector round to floor

1

VFPU

vec_trunc

vrfiz

vector truncate

1

VFPU

vec_re

vrefp

vector reciprocal estimate

1

VFPU

vec_rsqrte

vrsqrtefp

vector reciprocal square root estimate

1

VFPU

vec_loge

vlogefp

vector log estimate

1

VFPU

vec_expte

vexptefp

vector raised to the exponent estimate

1

VFPU

vec_ctf

VCIUux

vector convert from fixed-point word

2

VFPU

VCIUsx

vec_cts

vctsxs

vector convert to signed fixed-point word saturate

2

VFPU

vec_ctu

vctuxs

vector convert to unsigned fixed-point word saturate

2

VFPU

Logical Instructions

vec_and

vand

vector logical AND

2

VSIU

vac_andc

vandc

vector logical AND with complement

2

VSIU

vec_or

vor

vector logical OR

2

VSIU

vec_nor

vnor

vector logical NOR

2

VSIU

vec_xor

vxor

vector logical XOR

2

VSIU

Compare Instructions *

vec_cmpeq

vcmpequb

vector compare equal-to

2

VSIU

vcmpequh

vcmpequw

vcmpeqfp

VSIU VFPU

vec_cmpge

vcmpgefp

vector compare greater-than-or-equal-to

2

VSIU VFPU

vec_cmpgt

vcmpgtub

vector compare greater-than

2

VSIU

vcmpgtsb

vcmpgtuh

vcmpgtsh

vcmpgtuw

vcmpgtsw

vcmpgtfp

VSIU VFPU

vec_cmple

vcmpgefp

vector compare less-than-or-equal-to

2
VSIU VFPU

vec_cmplt

vcmpgtub

vector compare less-than

2
VSIU

vcmpgtsb

vcmpgtuh

vcmpgtsh

vcmpgtuw

vcmpgtsw

vcmpgtfp

VSIU VFPU

vec_all_eq

vcmpequb.

vector compare all equal-to

2

VSIU+Rc

vec_all_ne

vcmpequh.

vector compare all not equal-to

2

VSIU+Rc

vec_any_eq

vcmpequw.

vector compare any equal-to

2

VSIU+Rc

vec_any_ne

vcmpeqfp.

vector compare any not equal-to

2

VSIU+Rc VFPU+Rc

vec_all_ge

vcmpgtub.

vector compare all greater-than-or-equal-to

2

VSIU+Rc

vec_all_le

vcmpgtsb.

vector compare all less-than-or-equal-to

2

VSIU+Rc

vec_any_ge

vcmpgtuh.

vector compare any greater-than-or-equal-to

2

VSIU+Rc

vec_any_le

vcmpgtsh.

vector compare any less-than-or-equal-to

2

VSIU+Rc

vcmpgtuw.

2
VSIU+Rc

vcmpgtsw.

2
VSIU+Rc

vcmpgefp.

2
VSIU+Rc VFPU+Rc

vec_all_gt

vcmpgtub.

vector compare all greater-than

2

VSIU+Rc

vec_all_lt

vcmpgtsb.

vector compare all less-than

2

VSIU+Rc

vec_any_gt

vcmpgtuh.

vector compare any greater-than

2

VSIU+Rc

vec_any_lt

vcmpgtsh.

vector compare any less-than

2

VSIU+Rc

vcmpgtuw.

2
VSIU+Rc

vcmpgtsw.

2
VSIU+Rc

vcmpgtfp.

2
VSIU+Rc VFPU+Rc

vec_all_nan

vcmpeqfp.

vector compare all nan

1

VSIU+Rc VFPU+Rc

vec_all_numeric

vector compare all numeric

1

vec_any_nan

vector compare any nan

1

vec_any_numeric

vector compare any numeric

1

vec_all_nge

vcmpgefp.

vector compare all not greater-than-or-equal-to

2

VSIU+Rc VFPU+Rc

vec_all_nle

vector compare all not less-than-or-equal-to

2

vec_any_nge

vector compare any not greater-than-or-equal-to

2

vec_any_nle

vector compare any not less-than-or-equal-to

2

vec_all_ngt

vcmpgtfp.

vector compare all not greater-than

2

VSIU+Rc VFPU+Rc

vec_all_nlt

vector compare all not less-than

2

vec_any_ngt

vector compare any not greater-than

2

vec_any_nlt

vector compare any not less-than

2

vec_cmpb

vcmpbfp.

vector compare bounds float

2

VSIU+Rc VFPU+Rc

vec_all_in

vector compare bounds float in

2

vec_any_out

vector compare bounds float out

2

Execution units in bold are for the PowerPC 7450 and 7455.

* In the Compare instructions, some areas of the table have a different background shade than the others. This indicates that any of the C language intrinsics may generate any of the assembly instructions in the shaded area, as determined by the argument type(s).

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